VLSI Design Questions: Electronics Engineering MCQs

VLSI Design Questions. Part 2 of Multiple Choice Questions related to VLSI Design in Electronics Engineering. This Part includes 25 Multiple Choice Questions.


VLSI Design Questions


In the synthesis process, the load attribute specifies the existing amount of _________ load on a particular output signal ??

a. Inductive
b. Resistive
c. Capacitive
d. All of the above


Register transfer level description specifies all of the registers in a design & ______ logic between them ??

a. Sequential
b. Combinational
c. Both a and b
d. None of the above


Which among the following is an output generated by the synthesis process ??

a. Attributes & Library
b. RTL VHDL description
c. Circuit constraints
d. Gate-level netlist


Which among the following is not a characteristic of ‘Event-driven Simulator’ ??

a. Identification of timing violations
b. Storage of state values & time information
c. Time delay calculation
d. No event scheduling


Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of target signals periodically irrespective of any events ??

a. Event-driven Simulator
b. Cycle-based Simulator
c. Both a and b
d. None of the above


Electronics Engineering MCQs


In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator ??

a. Compilation
b. Elaboration
c. Initialization
d. Execution


Which type of simulation mode is used to check the timing performance of a design ??

a. Behavioural
b. Switch-level
c. Transistor-level
d. Gate-level


Which data type in VHDL is non-synthesizable & allows the designer to model the objects of dynamic nature ??

a. Scalar
b. Access
c. Composite
d. File


In VHDL, which object/s is/are used to connect entities together for the model formation ??

a. Constant
b. Variable
c. Signal
d. All of the above


In Net-list language, the net-list is generated _______ synthesizing VHDL code ??

a. Before
b. At the time of (during)
c. After
d. None of the above


VLSI Design Questions


Among the VHDL features, which language statements are executed at the same time in parallel flow ??

a. Concurrent
b. Sequential
c. Net-list
d. Test-bench


In VLSI design, which process deals with the determination of resistance & capacitance of interconnections ??

a. Floorplanning
b. Placement & Routing
c. Testing
d. Extraction


_________ is the fundamental architecture block or element of a target PLD ??

a. System Partitioning
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation


Which among the following is a process of transforming design entry information of the circuit into a set of logic equations ??

a. Simulation
b. Optimization
c. Synthesis
d. Verification


The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________ ??

a. Waveform Editor
b. Waveform Estimator
c. Waveform Simulator
d. Waveform Evaluator


VLSI Design Questions


Why are the multiple stuck-at-fault models preferred for DUT ??

a. Because single stuck-at fault model is independent of design style & technology
b. Because single stuck-at tests cover a major % of multiple stuck-at faults & unmodeled physical defects
c. Because the complexity of test generation is reduced to a greater extent in multiple stuck-at fault models
d. All of the above


Which type/s of stuck-at fault model exhibit/s the reduced complexity level of test generation ??

a. Single
b. Multiple
c. Both a and b
d. None of the above


Stuck open (off) fault occur/s due to _________ ??

a. An incomplete contact (open) of the source to drain node
b. Large separation of a drain or source diffusion from the gate
c. Both a and b
d. None of the above


An ideal op-amp has ________ ??

a. Infinite input resistance
b. Infinite differential voltage gain
c. Zero output resistance
d. All of the above


On the basis of an active load, which type of inverting CMOS amplifier represents low gain with highly predictable small and large signal characteristics ??

a. Active PMOS load inverter
b. Current source load inverter
c. Push-pull inverter
d. None of the above


VLSI Design Questions


In MOS devices, the current at any instant of time is ______ of the voltage across their terminals ??

a. constant & dependent
b. constant & independent
c. variable & dependent
d. variable & independent


For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS ??

a. Series
b. Parallel
c. Both series and parallel
d. None of the above


In the pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output ??

a. 1
b. 0
c. Both a and b
d. None of the above


In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value ??

a. Highest
b. Average
c. Lowest
d. None of the above


In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density ??

a. Placement
b. Global Routing
c. Detailed Routing
d. All of the above


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