VLSI Design MCQs: Electronics Engineering MCQs

VLSI Design MCQs. Multiple Choice Questions related to VLSI Design Technology in Electronics. This Part includes 20 Multiple Choice Questions.

 

VLSI Design MCQs

 

Which among the following faults occur/s due to physical defects ??

a. Process variations & abnormalities
b. Defects in silicon substrate
c. Photolithographic defects
d. All of the above

 

Which among the following is regarded as an electrical fault ??

a. Excessive steady-state currents
b. Delay faults
c. Bridging faults
d. Logical stuck-at-0 or stuck-at-1

 

In testability, which terminology is used to represent or indicate the formal evidence of correctness ??

a. Validation
b. Verification
c. Simulation
d. Integration

 

Which among the following is/are regarded as an/the active resistor/s b ??

a. MOS diode
b. MOS transistor
c. MOS switch
d. All of the above

 

In MOS switch, clock feedthrough effect is also known as __________ ??

A. charge injection
B. charge feedthrough
C. charge carrier
D. charge ejaculation

a. A & B
b. B & C
c. C & D
d. B & D

 

Which among the following can be regarded as an/the application/s of MOS switch in an IC design ??

a. Multiplexing & Modulation
b. Transmission gate in digital circuits
c. Simulation of a resistor
d. All of the above

 

Electronics Engineering MCQs

 

In DIBL, which among the following is/are regarded as the source/s of leakage ??

a. Subthreshold conduction
b. Gate leakage
c. Junction leakage
d. All of the above

 

In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials ??

a. Increases
b. Remains constant
c. Decreases
d. None of the above

 

Which type of MOSFET exhibits no current at zero gate voltage ??

a. Depletion MOSFET
b. Enhancement MOSFET
c. Both a and b
d. None of the above

 

Increase in the physical distance of H-tree _________ the skew rate ??

a. Increases
b. Stabilizes
c. Decreases
d. All of the above

 

Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points ??

a. H tree
b. Balanced tree clock network
c. Both a and b
d. None of the above

 

VLSI Design MCQs

 

Before the commencement of design, the clocking strategy determines __________ ??

a. Number of clock signals necessary for routing throughout the chip
b. The number of transistors used per storage requirement
c. Power dissipated by chip & the size of chip
d. All of the above

 

Which programming technology is/are predominantly associated with SPLDs and CPLDs ??

a. EPROM
b. EEPROM
c. FLASH
d. All of the above

 

In fusible link technologies, the undesired fuses are removed by the pulse application of _____ voltage & current to device input ??

a. Low
b. Moderate
c. High
d. All of the above

 

An Antifuse programming technology is predominantly associated with _____ ??

a. SPLDs
b. FPGAs
c. CPLDs
d. All of the

 

Hold time is defined as the time required for the data to ________ after the triggering edge of clock ??

a. Increase
b. Decrease
c. Remain stable
d. All of the above

 

VLSI Design MCQs

 

The time required for an input data to settle _____ the triggering edge of the clock is known as ‘Setup Time’ ??

a. Before
b. During
c. After
d. All of the above

 

The output of sequential circuit is regarded as a function of time sequence of __________ ??
A. Inputs
B. Outputs
C. Internal States
D. External States

a. A & D
b. A & C
c. B & D
d. B & C

 

Which type of digital systems exhibits the necessity for the existence of at least one feedback path from output to input ??

a. Combinational System
b. Sequential system
c. Both a and b
d. None of the above

 

Which attribute in the synthesis process specifies the resistance by controlling the quantity of current it can source ??

a. Load attribute
b. Drive attribute
c. Arrival time attribute
d. All of the above

 

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