VLSI Design MCQs Part 3: Electronics Engineering MCQs

VLSI Design MCQs Part 3. Part 3 of VLSI Design MCQs including 30 Multiple Choice Questions And Answers.

VLSI Design MCQs Part 3

 

Basically, observability of an internal circuit node is a degree to which one can observe that node at the _______ of an integrated circuit ??

a. Inputs
b. Outputs
c. Both a and b
d. None of the above

 

High observability indicates that ________ number of cycles are required to measure the output node value ??

a. More
b. Equal
c. Less
d. None of the above

 

Due to the limitations of the testers, the functional test is usually performed at speed _______ the target speed ??

a. Lower than
b. Equal to
c. Greater than
d. None of the above

 

Which among the following is/are responsible for the occurrence of ‘Delay Faults’ ??

a. Variations in circuit delays & clock skews
b. Improper estimation of on-chip interconnects & routing delays
c. Aging effects & opens in metal lines connecting parallel transistors
d. All of the above

 

Which among the following serves as an input stage to most of the op-amps due to its compatibility with IC technology ??

a. Differential amplifier
b. Cascode amplifier
c. Operational transconductance amplifiers (OTAs)
d. Voltage operational amplifier

 

Engineering MCQs

 

PSSR can be defined as the product of the ratio of change in supply voltage to change in the output voltage of op-amp caused by the change in power supply & _______ of op-amp ??

a. Open-loop gain
b. Closed-loop gain
c. Both a and b
d. None of the above

 

According to the principle of the current mirror, if gate-source potentials of two identical MOS transistors are equal, then the channel currents should be _______ ??

a. Equal
b. Different
c. Both a and b
d. None of the above

 

In a two-stage op-amp, what is the purpose of compensation circuitry ??

a. To provide high gain
b. To lower output resistance & maintain large signal swing
c. To establish a proper operating point for each transistor in its quiescent state
d. To achieve stable closed-loop performance

 

In accordance with the scaling technology, the total delay of the logic circuit depends on ______ ??

a. The capacitor to be charged
b. The voltage through which capacitance must be charged
c. Available current
d. All of the above

 

In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance ??

a. Static dissipation
b. Dynamic dissipation
c. Both a and b
d. None of the above

 

VLSI Design MCQs Part 3

 

In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________ gate ??

a. Driven
b. Receiving
c. Both a and b
d. None of the above

 

Which factor/s play/s a crucial role in determining the speed of the CMOS logic gate ??

a. Load capacitance
b. Supply voltage
c. The gain factor of MOS
d. All of the above

 

The power consumption of static CMOS gates varies with the _____ of power supply voltage ??

a. square
b. cube
c. fourth power
d. 1/8th power

 

In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count ??

a. Input pad design
b. Output pad design
c. Three state pad design
d. All of the above

 

Maze routing is used to determine the _______path for a single wire between a set of points if any path exists ??

a. Shortest
b. Average
c. Longest
d. None of the above

 

VLSI Design MCQs Part 3

 

Maze routing is also known as ________ ??

a. Viterbi’s algorithm
b. Lee/Moore algorithm
c. Prim’s algorithm
d. Quine-McCluskey algorithm

 

Which level of routing resources are supposed to be the dedicated lines allowing the output of each tile to connect directly to every input of eight surrounding tiles ??

a. Ultra-fast local resources
b. Efficient long-line resources
c. High speed, very long-line resources
d. High-performance global networks

 

In spartan-3 family architecture, which programmable functional element accepts two 18 bit binary numbers as inputs and computes the product ??

a. Configurable Logic Blocks
b. Input-Output Blocks
c. Block RAM
d. Multiplier Blocks

 

An anti-fuse element initial provides ______ between two conductors in absence of the application of sufficient programming voltage ??

a. Conduction
b. Insulation
c. Both a and b
d. None of the above

 

Which type of CPLD packaging comprises pins on all four sides that wrap around the edges of the chip ??

a. Plastic-Leaded Chip Carrier (PLCC)
b. Quad Flat Pack (QFP)
c. Ceramic Pin Grid Array (PGA)
d. Ball Grid Array (BGA)

 

VLSI Design MCQs Part 3

 

In Gray coding, when the state machine changes state, ______ bit/s in the state vector changes the value ??

a. one
b. two
c. four
d. eight

 

Which UART component/s divide/s the system clock to provide the bit clock with the period equal to the one-bit time and Block x 8 ??

a. Baud Rate Generator
b. Transmitter Section
c. Receiver Section
d. All of the above

 

If a port is declared as a buffer, then which problem is generated in hierarchical design due to mapping with the port of buffer mode of other entities only ??

a. Structural Modeling
b. Functional Modeling
c. Behavioral Modeling
d. Data Flow Modeling

 

Why is the use of mode buffer prohibited in the design process of synthesizer ??

a. To avoid mixing of clock edges
b. To prevent the occurrence of glitches & metastability
c. Because critical path has a preference in placement
d. Because Maximum ASIC vendors fail to support mode buffer in libraries

 

What is/are the necessity/ies of the Simulation Process in VHDL ??

a. Requirement to test designs before implementation & usage
b. Reduction of development time
c. Decrease the time to market
d. All of the above

 

VLSI Design MCQs Part 3

 

Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the _________ path delay between consecutive flip-flops ??

a. shortest
b. average
c. longest
d. unpredictable

 

An Assert is ______ command ??

a. Sequential
b. Concurrent
c. Both a and b
d. None of the above

 

The ‘next’ statements skip the remaining statement in the ________ iteration of loop and execution starts from the first statement of the next iteration of the loop ??

a. Previous
b. Next
c. Current (present)
d. None of the above

 

Which among the following functions are performed by MSI category of IC technology ??

a. Gates, Op-amps
b. Microprocessor/A/D
c. Filters
d. Memory/DSP

 

Which among the following EDA tool is available for design simulation ??

a. OrCAD
b. ALDEC
c. Simucad
d. VIVElogic

 

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