Microcontroller Interview Questions: Electronics Engineering

Microcontroller Interview Questions. MCQs related to Microcontrollers Interview Questions in Electronics Engineering.


Microcontroller Interview Questions



Consider the following statements. Which of them is /are incorrect ??

a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
c. During the occurrence of an interrupt, the GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.

a. A & B
b. C & D
c. Only A
d. Only C


Which bit-register pair plays a significant role in configuring the rising or falling edge triggering levels in external interrupts of PIC 16C61/71 ??

a. INTF bit – INTCON register
b. INTEDG bit – OPTION register
c. INT bit -INTCON register
d. INTE bit – OPTION register


What kind of external edge-sensitive interrupt is generated due to the transition effect at pin RBO/INT ??

a. INT
b. RBO
d. All of the above


Which condition results in setting the GIE bit of INTCON automatically ??

a. Execution of retfie instruction at the beginning of ISR
b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit


Which among the below-specified combination of interrupts belong to the category of the PIC 16C61 / 71 ??

a. External, Timer/Counter & serial Port Interrupts
b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts


Electronics MCQs



What is the purpose of acquiring two different bits from the INTCON register for performing any interrupt operation in PIC 16C61 / 71 ??

a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
d. None of the above


Which digital operations are performed over the detected mismatch outputs with an intention to generate a single output RB port change output ??

a. OR
b. AND
c. EX-OR


When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of ‘interrupt on change’ ??

a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs


Which bit/s should be necessarily cleared in the OPTION (SFR) register in order to turn on the weak internal pull-ups of port B ??

a. RPO
d. All of the above


When does it become possible for a bit to get accessed from bank ‘0’ in the direct addressing mode of PICs ??

a. Only when RPO bit is set ‘zero’
b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict


Microcontroller Interview Questions


Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register ??

a. GIE


Where is the exact specified location of an interrupt flag associated with an analog-to-digital converter ??



Where are the Prescaler assignments applied with usage of PSA bit ??

a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer


Which bit of the OPTION register has the potential to decide the falling or rising edge sensitivity for the external interrupt INT ??

c. PSA
d. RTS


Which bank of RFS has a provision of addressing the status register ??

a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2


Microcontroller Interview Questions


Which register acts as an input-output control as well as data direction register for PORTA in bank 2 of RFS ??

a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)


Which among the below-specified registers are addressable only from bank1 of RFS ??

a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)


Which flags of the status register are most likely to get affected by the single-cycle increment and decrement instructions ??

a. P Flags
b. C Flags
c. OV Flags
d. Z Flags