# Electronics Engineering MCQ

important Electronic Engineering (MCQ) questions with answers and explanations for your placement tests and job interviews. Covering topics like Signals and Systems, DSP, VLSI, Embedded Processors, IC, Optical Fiber, Mobile Communication, Microcontrollers, etc, these solved MCQ and numerical are useful for campus placement of Electronic Engineering freshers, university exams, job interviews, viva and competitive exams like GATE, IES, PSU, NET/SET/JRF, UPSC, and diploma.

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## Applications Of Microcontroller: MCQs On Microcontroller

Applications Of Microcontroller. This section has MCQs related to Microcontrollers And Its Applications.

## Applications Of Microcontroller

Match the following ??

a. JC rel ——————– 1. Jump if direct bit is set & clear bit
b. JNC rel —————— 2. Jump if direct bit is set
c. JB bit, rel ————— 3. Jump if direct bit is not set
d. JBC bit, rel ———— 4. Jump if carry is set
e. JNB bit, rel ————- 5. Jump if carry is not set

a. A-3, B-2, C-1, D-4, E-5
b. A-5, B-2, C-4, D-1, E-3
c. A-5, B-4, C-3, D-2, E-1
d. A-4, B-5, C-2, D-1, E-3

Match the following instruction mnemonics with their description ??

a. CJNE A,direct,rel ———— 1. Compare immediate to indirect and Jump if not equal
b. CJNE A,#data,rel ———— 2. Compare direct byte to accumulator and Jump if not equal
c. CJNE @Ri, #data,rel ——- 3. Compare immediate to register and Jump if not equal
d. CJNE Rn, # data rel ——– 4. Compare immediate to accumulator and Jump if not equal

a. A-1, B-2, C-3, D-4
b. A-2, B-4, C-1, D-3
c. A-4, B-3, C-2, D-1
d. A-2, B-4, C-3, D-1

How does the microcontroller communicate with the external peripherals/memory ??

a. via I/O ports
b. via register arrays
c. via memory
d. All of the above

Which functioning element of microcontroller generate and transmit the address of instruction to memory through internal bus ??

a. Instruction Decoding Unit
b. Timing and Control Unit
c. Program Counter
d. Arithmetic Logic Unit

Which instructions contribute to an effective adoption or utilization of stack memory which usually plays a crucial role in storage of intermediate results ??

a. ACALL
b. RETI
c. PUSH & POP
d. All of the above

Applications Of Microcontroller

What is the status of stack pointer for the execution of PUSH and POP operations ??

a. It gets post-decremented for PUSH & pre-incremented for POP
b. It gets pre-incremented for PUSH & post-decremented for POP
c. It gets pre-incremented for PUSH as well as POP
d. It gets post-decremented for PUSH as well as POP

Which flag allow to carry out the signed as well as unsigned addition and subtraction operations ??

a. CY
b. OV
c. AC
d. F0

What is the correct chronological order of the following steps involved in the LCALL operation ??

2. Increment of the program counter by value ‘3’
3. Storage of the higher byte of program counter on the stack
4. Increment of the stack pointer by value’1′
5. Storage of the lower byte of program counter on the stack
6. Increment in the value of stack pointer

a. 5, 3, 1, 6, 2, 4
b. 1, 3, 2, 5, 4, 6
c. 2, 4, 5, 6, 3, 1
d. 5, 3, 6, 2, 4, 1

Consider the below mentioned statements. Which among them is /are approved to be incorrect in case of calling instructions of program branching ??

a. Absolute Calls instructions specify 11-bit address and calling subroutine within 2K program memory block
b. Long call instructions specify 16-bit address and subroutine anywhere within 64K program memory block
c. Short call instructions specify 16-bit address and subroutine within 4K program memory block
d. All long call and short call instructions specify 11 bit address and the calling subroutine within 16K program memory block

a. Only A
b. B & D
c. A & C
d. C & D

Which among the category of program branching instructions allow 16-bit address to be specified & can jump anywhere within 64K block of program memory ??

a. Long jumps (LJMP)
b. Short jumps (SJMP)
c. Absolute jumps (AJMP)
d. All of the above

Applications Of Microcontroller

What is the possible range of transfer control for 8-bit relative address especially in 2’s complement form with respect to the first byte of preceding instruction ??

a. -115 to 132 bytes
b. -130 to 132 bytes
c. -128 to 127 bytes
d. -115 to 127 bytes

Which among the single operand instructions complement the accumulator without affecting any of the flags ??

a. CLR
b. SETB
c. CPL
d. All of the above

Which rotate instruction has an ability to modify CY flag by moving the bit-7 & bit-0 respectively to an accumulator ??

a. RR & RL
b. RLC & RRC
c. RR & RRC
d. RL & RLC

Which form of instructions also belong to the category of logical instructions in addition to bitwise logical instructions ??

a. Single-operand instructions
b. Rotate instructions
c. Swap instructions
d. All of the above

What can be the oscillator period for the multiplication operation of A & B in accordance to 16-bit product especially in B:A registers ??

a. 12
b. 24
c. 36
d. 48

Applications Of Microcontroller

How many bytes are supposed to get occupied while subtracting indirect RAM from an accumulator along with borrow under the execution of SUBB A, @Ri ??

a. 1
b. 2
c. 3
d. 4

What does the instruction XCHD A, @Ri signify during the data transfer in the program execution ??

a. Exchange of register with an accumulator
b. Exchange of direct byte with an accumulator
c. Exchange of indirect RAM with an accumulator
d. Exchange of low order digit indirect RAM with an accumulator

Which instruction should be adopted for moving an accumulator to the register from the below-mentioned mnemonics ??

a. MOV A, Rn
b. MOV A, @ Ri
c. MOV Rn, A
d. MOV direct, A

What kind of PSW flags remain unaffected by the data transfer instructions ??

a. Auxillary Carry Flags
b. Overflow Flags
c. Parity Flags
d. All of the above

How many single-byte, two-byte and three-byte instructions are supported by MCS-51 from the overall instruction set ??

a. 55 – single byte, 35 two-byte & 21 three-byte instructions
b. 50 – single byte, 30 two-byte & 31 three-byte instructions
c. 42 – single byte, 45 two-byte & 24 three-byte instructions
d. 45 – single byte, 45 two-byte & 17 three-byte instructions

Applications Of Microcontroller

What does the symbol ‘#’ represent in the instruction MOV A, #55H ??

a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype

Which base-register is preferred for address calculation of a byte that is to be accessed from program memory by base-register plus register-indirect addressing mode ??

a. DPTR
b. PSW
c. PCON
d. All of the above

Which bits of opcode specify the type of registers to be used in the register addressing mode ??

a. LSB
b. MSB
c. Both a & b
d. None of the above

Which byte has the capability to interrupt the slave when SM2 bit is assigned to be ‘1’ after the initialization process in the multiprocessor mode of communication ??

b. Data byte
c. Both a & b
d. None of the above

How does it become possible for 9th bit to differentiate the address byte from the data byte during the data transmission process in multiprocessor communication ??

a. By recognizing 9th bit as ‘1’ for address byte & ‘0’ for data byte
b. By recognizing 9th bit as ‘0’ for address byte & ‘1’ for data byte
c. By recognizing 9th bit as ‘1’ for address as well as data bytes
d. By recognizing 9th bit as ‘0’ for address as well as data bytes

## Microcontroller And Its Application MCQ: Microcontroller Q&A

Microcontroller And Its Application MCQ. This section has 25 advanced Multiple Choice Questions on Microcontrollers and Its Applications.

## Microcontroller And Its Application MCQ

What are the essential tight constraints related to the design metrics of an embedded system ??

a. Ability to fit on a single chip
b. Low power consumption
c. Fast data processing for real-time operations
d. All of the above

What is the maximum device handling capacity of serial standard protocol RS485 ??

a. 8
b. 10
c. 16
d. 32

What does an IC that initiate or enable the data transfer on bus can be regarded as, in accordance to the I2c protocol specifications ??

a. Bus Master
b. Bus Slaves
c. Bus Drivers
d. Bus Data Carriers

Which mechanism automates the enabling of RS485 transceiver with an elimination of hardware handshake line during each time of the data transmission ??

a. RTS Control
b. Send Data Control
c. Tri-State Control
d. Bit-wise Enable Timing Control

Which protocol standard of serial communication specify the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration ??

a. RS232
b. RS2485
c. RS422
d. RS423

Microcontroller And Its Application MCQ

Which among the below stated lines represent the handshaking variant usually and only controlled by the software in the handshaking process ??

a. XON/ XOFF
b. DCD & GND
c. TxD & RxD
d. All of the above

Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232 ??

a. CD & IR
b. DSR & DTR
c. RTS & CTS
d. None of the above

Which characteristics of an embedded system exhibit the responsiveness to the assortments or variations in system’s environment by computing specific results for real-time applications without any kind of postponement ??

a. Single-functioned Characteristics
b. Tightly-constraint Characteristics
c. Reactive & Real-time Characteristics
d. All of the above

Which abstraction level undergo the compilation process by converting a sequential program into finite-state machine and register transfers while designing an embedded system ??

a. System
b. Behaviour
c. RT
d. Logic

Match the following registers with their functions ??

a. Line Status Register ——————– 1. Set Up the communication parameters
b. Line Control Register —————— 2. Sharing of similar addresses
c. Transmit & Receive Buffers ——— 3. Status Determination of Tx & Rr

a. A-2, B-1, C-3
b. A-1, B-2, C-3
c. A-3, B-1, C-2
d. A-3, B-2, C-1

Microcontroller And Its Application MCQ

Which feature deals with the fetching of next instruction during the execution of current instruction irrespective of the memory access ??

a. Fetching
b. Pre-fetching
c. Fetch & Decoding
d. All of the above

Which kind of multiplexing scheme is adopted by Von-Newman architecture especially for program and data fetching purposes ??

a. Time Division Multiplexing
b. Frequency Division Multiplexing
c. Statistical Time Division Multiplexing
d. Code Division

Which factors/parameters contribute to an effective utilization or adoption of Harvard architecture by most of the DSPs for streaming data ??

a. Greater memory bandwidth
b. Predictable nature of bandwidth
c. Both a & b
d. None of the above

Which architectural scheme has a provision of two sets for address and data buses between CPU and memory ??

a. Harvard architecture
b. Von-Neumann architecture
c. Princeton architecture
d. All of the above

Which register of current procedure resemble physically similar to the parameter register of called procedure during register to register operation in an overlapping window of RISC Processors ??

a. Local Register
b. Temporary Register
c. Parameter Register
d. All of the above

Microcontroller And Its Application MCQ

What does the compact and uniform nature of instructions in RISC processors facilitate to ??

a. Compiler optimization
b. Pipelining
c. Large memory footprints
d. None of the above

What are the significant designing issues/factors taken into consideration for RISC Processors ??

a. Simplicity in Instruction Set
b. Pipeline Instruction Optimization
c. Register Usage Optimization
d. All of the above

How are the address and data buses removed in external memory type of microcontrollers ??

a. Through demultiplexing by external latch & ALE signal
b. Through demultiplexing by external latch & DLE signal
c. Through multiplexing by external latch & DLE signal
d. Through multiplexing by external latch & ALE signal

External Memory Microcontrollers can overcome the limitations of insufficient in-built program and data memory by allowing the connections of external memory using ??

a. Serial Port Pins as address and data lines
b. Parallel Port Pins as address and data lines
c. Parallel Port Pins as address and control lines
d. Serial Port Pins as address and control lines

Which category of microcontrollers acquires the complete hardware configuration on its chip so as to run the particular application ??

a. Embedded Memory Microcontrollers
b. External Memory Microcontrollers
c. Both a & b
d. None of the above

Microcontroller And Its Application MCQ

Which microcontrollers offer the provisional and salient software features of fault handling capability, interrupt vector efficiency and versatile addressing ??

a. TMS 1000 (4 bit)
b. TMS 7500 (8 bit)
c. Intel 8096 (16 bit)
d. Intel 80960 (32 bit)

Which among the below stated statements does not exhibit the characteristic feature of 16-bit microcontroller ??

a. Large program & data memory spaces
b. High-speed
c. I/O Flexibility
d. Limited Control Applications

Which word size is approved to be of greater importance for performing the small computational tasks along with its storage usability feature adopted by ASCII code ??

a. 4-bit
b. 8-bit
c. 16-bit
d. 32-bit

Which minimum mode signal is used for demultiplexing the data and address lines with the assistance of an external latch in a microprocessor while accessing memory segment ??

a. INTA
b. DTE
c. HOLD
d. ALE

Why do the microprocessors possess very few bit manipulating instructions ??

a. Because they mostly operate on bits/ word data
b. Because they mostly operate on byte/word data
c. Both a & b
d. None of the above

## Microcontroller And Applications MCQ: Electronics MCQs

Microcontroller And Applications MCQ. This set contains 24+ MCQs on the topic of Microcontroller And Applications in Electronics Engineering.

## Microcontroller And Applications MCQ

Which component is replaced by an in-circuit emulator on the development board for testing purpose ??

a. RAM
b. I/O Ports

d. All of the above

EPROM Programming versions are of greater significance to designers for ??

a. Debugging of hardware prototype
b. Debugging of software prototype
d. All of the above

How many samples can be displayed before and after the trigger respectively if the trigger-pulse is delayed by center-trigger mode to display 1024 bit counts ??

a. 512 & 512 samples respectively
b. 512 & 1024 samples respectively
c. 1024 & 512 samples respectively
d. 1024 & 1024 samples respectively

Which keys are encoded for scan lines with ‘1101’ value (RB1 low) condition ??

a. 0, 4, 8, C
b. 1, 5, 9, D
c. 2, 6, A, E
d. 3, 7, B, F

Which mandatory contents can be visualized by the hexadecimal display format of a logic analyzer ??

a. Data Bus
c. Both a & b
d. None of the above

Microcontroller And Applications MCQ

Which lines are driven low under the software control during interfacing HEX keyboard with PIC 16F877 ??

a. Scan Lines
b. Return Lines
c. Both a & b
d. None of the above

Which type of triggering allow the trigger qualifier circuit to compare the input data word with the word programmed by the user in logic analyzer ??

a. Triggering from external input
b. Programmable Triggering
c. Both a & b
d. None of the above

What is the purpose of using Schmitt Trigger in the hardware circuit for key debouncing ??

a. Noise Elimination
b. Improvement in Noise Immunity
c. Increase in Noise Figure
d. Reduction in Noise Temperature

What is/are the possible way/s of displaying the data by logic analyzer ??

a. Logic state format
c. Timing diagram format
d. All of the above

Which is the an alternative mechanism of preventing the software to be dependent on several delay factors along with an optimum time proficiency of checking LCD status at the interfacing level ??

a. Polling of DB7 bit of the data bus
b. Updating the faster display in less time
c. Generalization of clock frequency and display module
d. All of the above

Microcontroller And Applications MCQ

Which operations are not feasible to perform by simulator programs in accordance with real-time programming ??

a. Memory Operations
b. I/O Operations
c. Register Operations
d. Debugging Operations

It is feasible for an in-circuit emulator to terminate at the middle of the program execution so as to examine the contents of ??

a. memory
b. registers
c. Both a & b
d. None of the above

It is a characteristic provision of some debuggers to stop the execution after each instruction because ??

a. it facilitates to analyze or vary the contents of memory and register
b. it facilitates to move the break point to a later point
c. it facilitates to rerun the program
d. it facilitates to load the object code program to system memory

Which development tool can facilitate the creation and modification of source programs in addition to assembly and higher-level languages ??

a. Editor
b. Assembler
c. Debugger
d. High-level language Compiler

What are the major form of functionalities associated to high-level language compilers ??

a. Generation of an application program
b. Conversion of generated code from higher level language to machine-level language
c. Both a & b
d. None of the above

Microcontroller And Applications MCQ

What kind of address/es is /are usually assigned to program by the linker adopted in an execution of assembler ??

b. Relative Address starting from unity
c. Relative Addresss starting from zero
d. None of the above

Which kind of assembler do not generate the programs in similar language as that used by micro-controllers by developing the program in high-level languages making them as machine independent ??

a. Macro Assembler
b. Cross Assembler
c. Meta Assembler
d. All of the above

The assembler list file generated by an assembler mainly includes ??

a. binary codes
b. assembly language statements
c. offset for each instruction
d. All of the above

Which development tool/program has the potential to allocate the specific addresses so as to load the object code into memory ??

b. Locator
c. Library

What is the maximum speed of operating frequency exhibited by SPI as compared to that of TWI ??

a. Less than 10 MHz
b. Greater than 10 MHz
c. Equal to 10 MHz
d. None of the above

Microcontroller And Applications MCQ

Which characteristic/s of two-wire interface (TWI) make it equally valuable in comparison to serial-peripheral interface (SPI) ??

a. Less number of pins on IC packages than SPI
b. It possesses formal standard unlike SPI
c. Slave Addressing before communication & better hardware control
d. All of the above

Which among the below stated salient feature/s of SPI contribute to the wide range of its applicability ??

a. Simple hardware interfacing
b. Full duplex communication
c. Low power requirement
d. All of the above

Which processor has the necessity of manual optimization for the generation of assembly language code especially for the embedded systems ??

a. RISC
b. CISC
c. Both a & b
d. None of the above

Which potential mode of operation indicate the frequent sending of byte to the slave corresponding to the reception of an acknowledge signal when it becomes desirable for the master to write to the slave during data transmission in I2C bus ??

a. Master in master-transmit mode & Slave in slave-receive mode
b. Slave in slave-transmit mode & Master in master-receive mode
c. Master in master-transmit mode as well as master-receive mode
d. Slave in slave-transmit mode as well as a slave-receive mode

What is the directional nature of two active wires SDA & SCL usually adopted in I2C Bus for carrying the information between the devices ??

a. Uni-directional
b. Bi-directional
c. Multi-directional
d. None of the above

## Microcontroller Viva Questions: Electronics Engineering

Microcontroller Viva Questions. 25 Multiple Choice Questions related to Viva and tests on the topic Microcontrollers in Electronics Engineering. For all related MCQs visit Microcontrollers And Its Applications

## Microcontroller Viva Questions

What is the rate of power-up delay provided by an oscillator start-up timer while operating at XT, LP, and HS oscillator modes ??

a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles

Generation of Power-on-reset pulse can occur only after ??

a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power-up mode
d. the detection of a current limiting factor

Which condition/s of MCLR (master clear) pin allows resetting the PIC ??

a. High
b. Low
c. Moderate
d. All of the above

Where do the contents of PCLATH get transferred in the higher location of the program counter while writing in PCL (Program Counter Latch) ??

a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit

Which among the below stated registers specify the address reachability within 7 bits of address independent of RP0 status bit register ??

a. PCL
b. FSR
c. INTCON
d. All of the above

Microcontroller Viva Questions

Which statement is precise in relation to FSR, INDF, and indirect addressing mode ??

a. Address byte must be written in FSR before executing INDF instruction in the indirect addressing mode
b. Address byte must be written in FSR after executing INDF instruction in the indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF instruction in the indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in the indirect addressing mode

a. Only A
b. Only B
c. Only A & B
d. A & D

Which status bits exhibit carry from lower 4 bits during 8-bit addition and are especially beneficial for BCD addition ??

a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above

The RPO status register bit has the potential to determine the effective address of ??

d. Indc. Watchdog Timer (WDT) exed Addressing Mode

Which among the below-mentioned bits specify the reset status of register in a readable format and are usually utilized in sleep mode of PIC ??

a. TO
b. PD
c. Both a & b
d. None of the above

How many RPO status bits are required for the selection of two register banks ??

a. 1
b. 2
c. 8
d. 16

Microcontroller Viva Questions

Which register/s is/are mandatory to get loaded at the beginning before loading or transferring the contents to corresponding destination registers ??

a. W
b. INDF
c. PCL
d. All of the above

Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide ??

a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)

Which timer/s possess an ability to prevent an endless loop hanging condition of PIC along with its own on-chip RC oscillator by contributing to its reliable operation ??

a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above

Which among the below specified major functionalities is/are associated with the programmable timers of PIC ??

a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs

a. Only C
b. C & D
c. A, B & D
d. A, B & C

Which among the below stated reasons is/are responsible for the selection of PIC implementation/design on the basis of Harvard architecture instead of Von-Newman architecture ??

a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program memory
d. All of the above

Microcontroller Viva Questions

Which operational feature of PIC allows it to reset especially when the power supply drops the voltage below 4V ??

a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above

What is the execution speed of instructions in PIC especially while operating at the maximum value of clock rate ??

a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs

Which flags are more likely to get affected in status registers by Arithmetic and Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution ??

a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above

How many clock pulses are confined by each machine cycle of Peripheral-Interface Controllers ??

a. 4
b. 8
c. 12
d. 16

What does the RAM location at 44H indicates about the seven-segment code ??

a. 7-segment code for the third character
b. 7-segment code for the fourth character
c. Display of select code for third display
d. Display of select code for fourth display

Microcontroller Viva Questions

How are the port pins of the microcontroller calculated for time-multiplexing types of display ??

a. 4 + number of digits to be displayed
b. 4 raised to the number of digits to be displayed
c. 4 – number of digits to be displayed
d. 4 x number of digits to be displayed

What is the purpose of blanking (BI) associated with the 7-segment display operations ??

a. To turn ON the display
b. To turn OFF the display
c. To pulse modulate the brightness of display
d. To pulse modulate the lightness of display

a. B & C
b. A & D
c. A & B
d. C & D

Which errors are more likely to get generated by conversion time and ADC resolution respectively in accordance to the digital signal processing ??

a. Sampling & Quantization Errors
b. Systematic & Random Errors
d. None of the above

Which pin/signal of ADC AD571 interfacing apprises the accomplishment of data reading in the microcontroller so as to indicate ADC to get ready for the next data sample ??

a. BLANK /CONVERT (high)
b. BLANK/DR (low)
d. All of the above

Which factors indicate the necessity of sample and hold circuits in the process of analog-to-digital conversion ??

a. Instantaneous variation in an input signal
b. Analog-to-digital conversion time
c. Both a & b
d. None of the above

## Microcontroller MCQ Questions: Electronics Engineering

Microcontroller MCQ Questions. 24+ Multiple Choice Questions regarding Microcontrollers in Electronics Engineering.

## Microcontroller MCQ Questions

Which bits assist in determining the I2C bit rate during the initialization process of the MSSP module in I2C mode ??

b. SSPBUF
c. Both a & b
d. None of the above

What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave mode by enabling SS pin control ??

a. 0000
b. 0100
c. 0010
d. 0001

Which bit of SSPCON must be necessarily set so as to enable the synchronization of serial port ??

a. WCOL
b. SSPOV
c. CKP
d. SSPEN

Which among the below stated conditions are selected by the SSPCON & SSPSTAT control bits ??

a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above

Which among the below-stated components should be filtered for determining the cut-off frequency corresponding to the PW period of the low-pass filter ??

a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components

Microcontroller MCQ Questions

How do the variations in an average value get affected by the PWM period ??

a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value

What would be the resolution value if oscillator and PWM frequencies are 16MHz and 2 MHz respectively ??

a. 2
b. 3
c. 4
d. 8

Why are the pulse width modulated outputs required in most of the applications ??

a. To control the average value of input variables
b. To control the average value of output variables
c. Both a & b
d. None of the above

Where does the comparison level occur for 16-bit contents in the compare mode operation ??

a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0

Which registers are adopted by CPU and peripheral modules so as to control and handle the operation of devices inhibited in RFS ??

a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above

Microcontroller MCQ Questions

How many bits are utilized by the instruction of direct addressing mode in order to address the register files in PIC ??

a. 2
b. 5
c. 7
d. 8

When does the special address 004H get automatically loaded into the program counter ??

a. After the execution of RESET action in program counter
b. After the execution of ‘goto Mainline ‘ instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value

What location is attributed to ‘goto Mainline’ instruction in the program memory of PIC 16C61 ??

a. 000H
b. 004H
c. 001H
d. 011H

How many bits are required for addressing 2K & 4K program memories of PIC 16C61 respectively ??

a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits

What is the executable frequency range of the High speed (HS) clocking method by using crystal/ ceramic/ resonator or any other external clock source ??

a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz

Microcontroller MCQ Questions

Which significant feature/s of crystal source contribute/s to its maximum predilection and utility as compared to other clock sources ??

a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above

Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock sources for operating at the range of 5- 200 kHz in PIC ??

a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)

What output is generated by OSC2 pin in PIC oscillator comprising RC components for synchronizing the peripherals with PIC microcontroller ??

a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1

What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in PIC ??

a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again

Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely unique and distinct from other microcontrollers ??

a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above

Microcontroller MCQ Questions

Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature ??

a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71

a. A & B
b. C & D
c. A & C
d. B & D

When does it become very essential to use the external RC components for the reset circuits ??

a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if the current limiting factor increases rapidly

Which program location is allocated to the program counter by the reset function in Power-on-Reset (POR) action modes ??

d. At any address reliable for reset operations

What is the purpose of using the start-up timers in an oscillator circuit of PIC ??

a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers

What kind of mode is favorable for MCLR pin for indulging in reset operations ??

a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode

## Microcontroller MCQ: Electronics Engineering Q & A

Microcontroller MCQ. Multiple Choice Questions and Answers on Microcontrollers in Electronics Engineering. This set has 18 MCQs related to Microcontrollers.

## Microcontroller MCQ

Where is the result stored after execution of increment and decrement operations over the special-purpose registers in PIC ??

a. File Register
b. Working Register
c. Both a & b
d. None of the above

Which instruction is applicable to set any bit while performing bitwise operation settings ??

a. bcf
b. bsf
c. Both a & b
d. None of the above

What does the ‘program idata’ section of data memory contain in C-18 Compiler ??

a. statically assigned/allocated initialized user variables
b. statically assigned /allocated uninitialized user variables
c. only executable instructions
d. variables as well as constants

In which aspects do the output functions specified in stdio.h differs from ANSI specified versions ??

a. Provision of MPLAB specific extensions
b. Floating-point Format Support
c. Data in Program Memory
d. All of the above

Which command-line option of compiler exhibits the banner comprising an overall number of errors, messages, warnings, and version number after an accomplishment of the compilation process ??

a. help
b. verbose
c. overlay
d. char

### MCQs

Which among the below assertions represent the salient features of PIC in C-18 compiler ??

b. Provision of supporting an inline assembly during the necessity of an overall control
c. Integration with MPLAB IDE for source-level debugging
d. All of the above

Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as DT (data lines) ??

a. TXSTA
b. RCSTA
c. Both a & b
d. None of the above

Which bit plays a salient role in defining the master or slave mode in the TXSTA register especially in synchronous mode ??

a. RSRC
b. CSRC
c. SPEN
d. SYNC

Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as DT (data lines) ??

a. TXSTA
b. RCSTA
c. Both a & b
d. None of the above

Which bit plays a salient role in defining the master or slave mode in the TXSTA register especially in synchronous mode ??

a. RSRC
b. CSRC
c. SPEN
d. SYNC

Microcontroller MCQ

What is the status of shift clock supply in a USART synchronous mode ??

a. Master-internally, Slave-externally
b. Master-externally, Slave-internally
c. Master & Slave (both) – internally
d. Master & Slave (both) – externally

How is the baud rate specified for high-speed (BRGH = 1) operation in an asynchronous mode ??

a. FOSC / 8 (X + 1)
b. FOSC / 16 (X + 1)
c. FOSC / 32 (X + 1)
d. FOSC / 64 (X + 1)

Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the data bits during the initialization process of USART in asynchronous mode ??

a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity

What is the purpose of a special function register SPBRG in USART ??

a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bit
d. All of the above

Where should the value of TX9 bit be loaded during the 9-bit transmission in an asynchronous mode ??

a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above

Microcontroller MCQ

How many upper bits of SSPSR is comparable to the address located in SSPADD especially after the shifting of 8 bits into SSPSR under the execution of START condition ??

a. 7
b. 8
c. 16
d. 32

Where does the baud rate generation occur and begins to count the bits required to get transmitted, after an execution (set) of BF flag ??

a. SCL line
b. SDA line
c. Both a & b
d. None of the above

Which command/s should be essentially written for I2C input threshold selection and slew rate control operations ??

a. SSPSTAT
b. SSPIF
c. ACKSTAT
d. All of the above

## Microcontroller Interview Questions: Electronics Engineering

Microcontroller Interview Questions. MCQs related to Microcontrollers Interview Questions in Electronics Engineering.

## Microcontroller Interview Questions

Consider the following statements. Which of them is /are incorrect ??

a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
c. During the occurrence of an interrupt, the GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.

a. A & B
b. C & D
c. Only A
d. Only C

Which bit-register pair plays a significant role in configuring the rising or falling edge triggering levels in external interrupts of PIC 16C61/71 ??

a. INTF bit – INTCON register
b. INTEDG bit – OPTION register
c. INT bit -INTCON register
d. INTE bit – OPTION register

What kind of external edge-sensitive interrupt is generated due to the transition effect at pin RBO/INT ??

a. INT
b. RBO
c. INTF
d. All of the above

Which condition results in setting the GIE bit of INTCON automatically ??

a. Execution of retfie instruction at the beginning of ISR
b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit

Which among the below-specified combination of interrupts belong to the category of the PIC 16C61 / 71 ??

a. External, Timer/Counter & serial Port Interrupts
b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts

### Electronics MCQs

What is the purpose of acquiring two different bits from the INTCON register for performing any interrupt operation in PIC 16C61 / 71 ??

a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
d. None of the above

Which digital operations are performed over the detected mismatch outputs with an intention to generate a single output RB port change output ??

a. OR
b. AND
c. EX-OR
d. NAND

When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of ‘interrupt on change’ ??

a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs

Which bit/s should be necessarily cleared in the OPTION (SFR) register in order to turn on the weak internal pull-ups of port B ??

a. RPO
b. RPBU
c. RBIF
d. All of the above

When does it become possible for a bit to get accessed from bank ‘0’ in the direct addressing mode of PICs ??

a. Only when RPO bit is set ‘zero’
b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict

Microcontroller Interview Questions

Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register ??

a. GIE
c. RBIE
d. TOIE

Where is the exact specified location of an interrupt flag associated with an analog-to-digital converter ??

a. INTCON
d. PCLATH

Where are the Prescaler assignments applied with usage of PSA bit ??

a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer

Which bit of the OPTION register has the potential to decide the falling or rising edge sensitivity for the external interrupt INT ??

a. RBPU
b. INTEDG
c. PSA
d. RTS

Which bank of RFS has a provision of addressing the status register ??

a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2

Microcontroller Interview Questions

Which register acts as an input-output control as well as data direction register for PORTA in bank 2 of RFS ??

a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)

Which among the below-specified registers are addressable only from bank1 of RFS ??

a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)

Which flags of the status register are most likely to get affected by the single-cycle increment and decrement instructions ??

a. P Flags
b. C Flags
c. OV Flags
d. Z Flags

## Microcontrollers Multiple Choice Questions: Electronics MCQ

Microcontrollers Multiple Choice Questions. This set includes 18 Multiple choice questions on Microcontrollers in Electronics Engineering.

## Microcontrollers Multiple Choice Questions

How does the pin RC2/CCP1 get configured while initializing the CCP module in the compare mode of operation ??

a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization

What is the fundamental role exhibited by the CCP module in compare mode in addition to timer 1 ??

a. To vary the pin status in accordance with the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels

The capture operation in counter mode is feasible when the mode of CCP module is ??

a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization

Which register is suitable for the corresponding count, if the measurement of pulse width is less than 65,535 μs along with the frequency of 4 MHz ??

a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register

What happens when the program control enters the Interrupt Service Subroutine (ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of CCP1 Module in capture mode ??

a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR

### Microcontrollers MCQs

What among the below-specified functions is related to PWM mode ??

a. Generation of an interrupt
b. Generation of a rectangular wave with programmable duty cycle with a user-assigned frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge

Which mode allows to deliver the contents of a 16-bit timer into an SFR on the basis of rising/falling edge detection ??

a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode

Which of the below-mentioned aspect issues are supported by capture/compare/PWM modules corresponding to the time in PIC 16F877 ??

a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above

The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated by ??

a. PCFG1 & PCG0
b. VREF
d. All of the above

What would be the value of the ADC clock source, if both the ADC clock bits are selected to be ‘1’ ??

a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC

Microcontrollers Multiple Choice Questions

Which bit is mandatory to get initiated or set for executing the process of analog to digital conversion in ADCON0 ??

c. Go/!Done

Which channel would be selected if the values of channel bits CHS0 & CHS1 are ‘1’ & ‘0’ respectively in ADC Status Register ??

a. AIN0
b. AIN1
c. AIN2
d. AIN3

Which bits play a crucial role in specifying the details or reasons associated with the system wake-up in WDT ??

a. PD & TO
b. C & Z
c. DC & RPO
d. All of the above

Which command enables the PIC to enter into the power-down mode during the operation of the watchdog timer (WDT) ??

a. SLEEP
b. RESET
c. STATUS
d. CLR

How much delay is required to synchronize the external clock at TOCKI in Timer ‘0’ of PIC 16C61 ??

a. 2-cycles
b. 4-cycles
c. 6-cycles
d. 8-cycles

Microcontrollers Multiple Choice Questions

How much time is required for conversion per channel if PIC 16C71 possesses four analog channels, each comprising of 8-bits ??

a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs

Where do the conversion interrupt flag (ADIF) end after an accomplishment of the analog-to-digital (ADC) conversion process ??

a. INTCON
c. OPTION
d. None of the above

What is the purpose of setting TOIE bit in INTCON along with GIE bit ??

a. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
d. None of the above

## Mobile Communication Advanced Questions: MCQs Set

Mobile Communication Advanced Questions. This set has 18 Multiple Choice Questions related to Mobile Communication in Electronics Engineering.

The advantages of FDMA over TDMA include ??

1. Division is simpler
2. Propagation delays are eliminated
3. Cheaper filters with less complicated logic functions
4. Linearity

a. 1, 2, and 3 are correct
b. 1 and 2 are correct
c. 1 and 4 are correct
d. All four are correct

a. Induced delays
b. Low spectral efficiency
c. Large spectrum required
d. Both a and b
e. Both b and c

TDMA is a multiple-access technique that has ??

a. Different users in different time slots
b. Each user is assigned unique frequency slots
c. Each user is assigned a unique code sequence
d. Each signal is modulated with a frequency modulation technique

a. Multiple users on single-channel
b. Single user on multiple channels as per demand
c. Multiple users on multiple channels at different time slots
d. Multiple users with coding techniques

### Electronics MCQs

In TDMA, the user occupies the whole bandwidth during transmission ??

a. True
b. False

The guard interval is provided in OFDM ??

a. To eliminate the need for pulse shaping filter
b. To eliminate ISI
c. High symbol rate
d. Both a and b
e. Both b and c

TDMA allows the user to have ??

a. Use of same frequency channel for same time slot
b. Use of same frequency channel for different time slot
c. Use of same time slot for different frequency channel
d. Use of different time slot for different frequency channels

The troubles that OFDM faces over other spread spectrum techniques are ??

1. Sensitivity to Doppler shift
2. Frequency synchronization problems
3. Time synchronization problems
4. Low efficiency due to guard intervals

a. 1, 2, and 3 are correct
b. 2 and 3 are correct
c. 1, 2, and 4 are correct
d. All the four are correct

GSM is an example of ??

a. TDMA cellular systems
b. FDMA cellular systems
c. CDMA cellular systems
d. SDMA cellular systems

Advantages of using OFDM include ??

1. Avoids complex equalizers
2. Low symbol rate and guard interval
3. Avoids ISI
4. Multiple users at the same frequency

a. 1, 2, and 3 are correct
b. 2 and 3 are correct
c. 1, 2, and 4 are correct
d. All four are correct

TDMA is employed with a TDMA frame that has a preamble. The preamble contains Address of the base station and subscribers ??

1. Synchronization information
2. Frequency allotted
3. Coded sequence

a. 1 and 2 are correct
b. 1, 2, and 3 are correct
c. 2 and 4 are correct
d. All four are correct

OFDM is a technique of ??

1. Encoding digital data
2. Multiple carrier frequencies
3. Wideband digital communication
4. 4G mobile communication

a. 1, 2, and 3 are correct
b. 2 and 3 are correct
c. 1, 2, and 4 are correct
d. All four are correct

CDMA is ??

2. Using the same communication medium
3. Every user stays at a certain narrowband channel at a specific time period
4. Each user has a unique PN code

a. 1, 2, and 3 are correct
b. 2 and 3 are correct
c. 1, 2, and 4 are correct
d. All four are correct

FHMA is ??

2. Using the same communication medium
3. Every user has assigned a unique frequency slot
4. Each user has a unique PN code

a. 1 and 2 are correct
b. 1, 2, and 4 are correct
c. 2 and 4 are correct
d. All four are correct

Global Positioning System uses ??

a. CDMA
b. TDMA
c. SDMA
d. FDMA

The advantages of using a CDMA technique over other spread spectrum techniques are ??

1. Increased capacity
2. Easier handoff
3. Better measure of security
4. Multiple users occupy different spectrum at a time

a. 1, 2, and 3 are correct
b. 2, 3, and 4 are correct
c. 1, 2, and 4 are correct
d. All the four are correct

1. The privacy due to unique codes
2. It rejects narrowband interference
4. Its ability to frequency reuse

a. 1, 2, and 3 are correct
b. 2 and 3 are correct
c. 1, 2, and 4 are correct
d. All four are correct

The wideband usage in CDMA helps in ??

1. Increased immunity to interference
2. Increased immunity to jamming
3. Multiple user access
4. Different spectrum allocation in different time slots

a. 1, 2, and 3 are correct
b. 2, 3, and 4 are correct
c. 1, 2, and 4 are correct
d. All the four are correct

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